Pro
Checking your session

G7 Fellow – High-Speed Interfaces & Clocking Strategy

Bangalore; Eindhoven

· full time

Posted Sep 17, 2026Availability needs checking · last checked Nov 6, 2026
Check my fit on this page

About this role

KEY RESPONSIBILITIES

TECHNOLOGY STRATEGY & ROADMAP LEADERSHIP

  • Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP.
  • Analyze current and future requirements across all NXP Business Lines and Product Lines.
  • Develop technology roadmaps aligned with market trends, customer needs, and product strategies.
  • Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.
  • Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position.

PORTFOLIO ANALYSIS & MAKE-OR-BUY DECISIONS

  • Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications.
  • Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities.
  • Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.
  • Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact.

CLOCKING & PLL TECHNOLOGY LEADERSHIP

  • Define company-wide clocking and synchronization strategies.
  • Drive the roadmap for next-generation clock generation and PLL solutions with focus on:
  • Low jitter
  • Low power
  • Small area
  • Scalability across process nodes
  • High-performance operation
  • Functional safety requirements
  • Lead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.

HIGH-SPEED INTERFACE ARCHITECTURE

  • Provide technical leadership for connectivity technologies including:
  • I3C
  • USB / eUSB
  • Ethernet
  • USXGMII
  • MIPI
  • DDR
  • PCIe
  • CXL
  • UCIe
  • Emerging chiplet interconnect technologies
  • Guide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.

INNOVATION & TECHNICAL EXCELLENCE

  • Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies.
  • Anticipate emerging industry trends and identify opportunities for NXP differentiation.
  • Drive benchmarking, technology assessments, and architectural studies.
  • Foster technical excellence and innovation across engineering communities.
  • Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.

More information about NXP in India...

#LI-9415

From NXP’s career feed. View the original listing