Sr Principal Design Engineer
BANGALORE
· full time
Posted Sep 1, 2025Availability needs checking · last checked Nov 3, 2026
Check my fit on this page About this role
AT CADENCE, WE HIRE AND DEVELOP LEADERS AND INNOVATORS WHO WANT TO MAKE AN IMPACT ON THE WORLD OF TECHNOLOGY.
12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
WE’RE DOING WORK THAT MATTERS. HELP US SOLVE WHAT OTHERS CAN’T.
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