Lead Design Engineer
BANGALORE
· full time
Posted May 28, 2026Source checked Nov 9, 2026
Check my fit on this page About this role
AT CADENCE, WE HIRE AND DEVELOP LEADERS AND INNOVATORS WHO WANT TO MAKE AN IMPACT ON THE WORLD OF TECHNOLOGY.
1. Proficient in Verilog coding and RTL design, data path designs,
2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
WE’RE DOING WORK THAT MATTERS. HELP US SOLVE WHAT OTHERS CAN’T.
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